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Assessment
of Advanced Flip-Chip Electronics Package
Test Assemblies Under Extreme Temperatures
Rajeshuni
Ramesham, NASA JPL/California Institute of Technology
Abstract FB250 and FB500 flip-chip boards have been assembled and subjected to extreme temperature thermal cycling in order to evaluate the robustness of this advanced packaging technology. The temperature range covers military specifications and the extreme Martian environment at various ramp rates. Resistance of the daisy chained flip chips has been monitored as a function of thermal cycling. Preliminary electrical resistance measurements have been reported; electrical tests to date have not shown significant change in resistance as a function of thermal cycling. However, the greater the number of thermal cycles, the more noticeable the change in the resistance of the daisy chained flip chips. No catastrophic failures were observed, even after 481 extreme temperature thermal cycles per electrical measurements. However, process qualification is required to optimize the flip-chip assembly.
Flip-Chip Test Boards With an increasing number of I/Os on integrated circuits and accompanying requirements for high performance, flip-chip type components have become a compelling technology. NASA will be one of their primary users, especially in the context of wide extreme temperature ranges. We have the ability to test boards for die specifications, bump pitches, and bump counts; both components and test boards are daisy chained for continuity. Figure 1 shows the optical photographs of the FB250 and FB500 test boards: High temperature FR4 (Tg = 176 oC) 0.031” thickness, copper conductor, Taiyo PSR-400 solder mask, FB250 board (10: 250 x 250 mil2 sites, pitch 18 mil, minimum line 6 mil, and maximum space 12 mil), and FB500 board (10: 500 x 500 mil2 sites, pitch 18 mil, minimum line 6 mil, and maximum space 12 mil).
Temperature Profile Figure 2 shows the temperature profile employed to perform the extreme temperature thermal cycling of the FB250 and FB500 flip-chip test boards.
Electrical Tests The resistance of the daisy chained FB250 and FB500 test boards (Figure 1) was measured as a function of thermal cycling performed in the various temperature ranges described above. Figures 3 and 4 show the experimental test data after thermal cycling. Detailed experimental data will be presented in the future.
X-ray Imaging and Surface Acoustic Microscopy This work will be performed shortly to identify failures in the flip-chip interconnects as a function of thermal cycling in an extreme temperature range. Electrical tests show that there is not significant change in resistance as a function of thermal cycling.
FB500 Bare chip inspection: The X-ray image of one chip is shown in Figure 5. Two opposite corners, depicted at the same magnification, show non-uniform solder bumping.
Solder wetting after reflow: Kester 6502 tacky flux with a shim of 35mm thickness was used for this build. The X-ray image of a solder joint after reflow is shown in Figure 6; this figure represents two opposite corners at the same magnification, showing different wetting results. The cross-section images of the two adjacent edges corresponding to Figure 6(b) are shown in Figure 7.
Underfill: Parameters for the underfill process are shown in Table 1. The CSAM images were obtained after underfill cure. One out of 40 chips was found with voids, which is shown in Figure 8. The middle line pattern with one-third of the edge length was used for dispensing. The void occurred close to the opposite edge.
FB250 Solder wetting after reflow: Kester 6502 tacky flux with a shim of 35mm thickness was used for this build. The X-ray image of a solder joint after reflow is shown in Figure 9. The shape of the solder joint indicates good wetting.
Underfill: Parameters for the underfill process are shown in Table 2. The CSAM images were obtained after underfill cure. Four out of 70 chips were found with voids, which are shown in Figure 10. The middle line pattern with one-third of the edge length was used for dispensing. The void occurred close to the opposite edge.
Conclusions Advanced packaging technology, such as flip-chip test boards (FB250 and 500), has been subjected to extreme temperature ranges that cover military specifications and the extreme Martian environment at various ramp rates. The greater the number of thermal cycles, the more noticeable the change in resistance of the daisy chained flip chips. No catastrophic failures were observed, even after 481 extreme temperature thermal cycles per electrical measurements. Process qualification is required to optimize the flip-chip assembly, which is clear from the X-ray and CSAM studies. X-ray and CSAM studies have not been made as of yet after thermal cycling and will be done shortly. After extensive testing for future space applications in the extreme temperature environments, it may be determined that the flip-chip advanced test assembly is a robust technology.
Acknowledgements This work has been supported by NEPP to assess the reliability of advanced interconnect and packaging technologies under extreme cold temperatures. I would like to thank Dr. Reza Ghaffarian for his encouragement and support.
Table 1. Parameters for underfill component FB500.
Table 2. Parameters for underfill component FB250.
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