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Packaging of High Temperature SiC Based Electronics

Liang-Yu Chen, Ohio Aerospace Institute
Liangyu.Chen@grc.nasa.gov
Robert S. Okojie, GRC/NASA
Philip G. Neudeck,GRC/NASA
Gary W. Hunter, GRC/NASA
Shun-Tien T. Lin, United Technologies Research Center
LinS@utrc.utc.com

Abstract

In order to establish a material system for packaging 500°C SiC microsystems, aluminum nitride (AlN) and aluminum oxide (Al₂O₃) were selected as packaging substrates, and gold (Au) thick-film materials were selected as substrate metallization material for electrical interconnection system (thick-film printed wires and thick-film metallization based wire-bond) and conductive die-attach interlayer. During a 1500-hour test in atmospheric oxygen with and without electrical bias, the electrical resistance of Au thick-film based interconnection system demonstrated low and stable electrical resistance at 500^°C. The electrical interconnection system was also tested in extreme dynamic thermal environment. A silicon carbide (SiC) Schottky diode was attached to ceramic substrate using Au thick-film material as the conductive bonding layer and was successfully tested at 500°C in air for more than 1000 hours. In addition to the electrical test of die-attach in static thermal environments, nonlinear finite element analysis (FEA) was used for thermal mechanical evaluation and optimization of the die-attach in a wide temperature range.

NASA is interested in using high temperature operable microsystems, including micro-electro-mechanical-systems (MEMS) and on-chip electronics, to characterize in-situ combustion environments of aerospace engines and the atmosphere of inner solar planets such as Venus. As an example, high temperature pressure sensor is one of NASA and aerospace industry’s ‘most wanted’ high temperature sensors for application in development of new generation of aerospace engines. The sensor and on-chip electronics must operate at temperatures up to 500°C, and the devices are always directly exposed to combustion species including oxygen in air, hydrocarbon/hydrogen in fuel, and catalytically poisoning species such as NO_x and SO_x in combustion exhaust. The temperature in the atmospheric environment of Venus is also as high as 500°C, and its gas ambience is corrosive. These operation environments can be summarized as high temperature, high dynamic pressure, and chemically corrosive. Various SiC semiconductor devices have been demonstrated to be operable at temperatures as high as 600°C [1,2], but only in a probe-station test environment partially because chip level packaging technology for high temperature (500°C and beyond) devices is still being developed. Core technologies needed for successful high temperature device packaging include high temperature operable electrical interconnection system and a conductive die-attach scheme.

MEMS devices, as they are identified, are both electrical and mechanical devices. Through micro-level mechanical operation, MEMS devices, as sensors, may transform mechanical, chemical, optical, magnetic, and other non-electrical parameters to electrical/electronic signals. As actuators, MEMS devices transform electrical/electronic signal into non-electrical/electronic operation. Therefore, compared to conventional integrated circuit (IC) packaging, the most distinct issue of high temperature MEMS packaging is to meet the thermal mechanical requirements imposed by the mechanical operability and reliability of MEMS devices in a wide temperature range. High temperature SiC piezoresistive pressure sensors is a good example to illustrate the thermal mechanical requirements for packaging high temperature MEMS: the sensing mechanism of this device depends on the mechanical deformation of the semiconductor resistors residing on a diaphragm fabricated by micro-machining. Therefore, this device is very sensitive to the thermal mechanical stress from the die-attach due to mismatches of coefficients of thermal expansion (CTEs) in the die material (such as SiC), the substrate material, and in the die-attaching material.

Since MEMS devices have very specific structure requirements with respect to their immediate packaging environment [3], it is expected that the design of MEMS packaging will be very device dependent. This is in contradiction to the conventional IC packaging practice in which a universal package design can accommodate many different ICs. In order to address the common needs of high temperature microsystem packaging, we first discuss the basic requirements for packaging materials. Based on the discussions on the material requirements, a gold thick-film metallization based 500°C operable electrical interconnection system and a thick-film material based conductive die-attach scheme are introduced. Following that the thermal mechanical evaluation and optimization of the die-attach are addressed by nonlinear finite element analysis (FEA).

A summary of basic requirements of the major materials needed for packaging high temperature microsystems may help to establish guidelines for material selections:

Substrates: Ceramics meet the basic requirements for substrate material to be operable at high temperatures since ceramic materials have excellent and stable chemical and electrical properties at high temperatures, especially, in corrosive gas ambience. After a substrate material is selected, a high temperature operable metallization scheme (both materials and processing) matching the substrate material must be identified or developed to provide electrical interconnection. In order to reduce the thermal mechanical stress of the die-attach structure, the CTE of substrate material must match that of the device material (such as SiC). The properties of substrate surface and the interfaces formed at high temperature with other packaging materials, such as the die-attach material, also become very important. At high temperatures, the surfaces of some ceramics gradually react with gas ambience, such as oxygen and water vapor, therefore, would exhibit changes in properties such as surface resistivity and surface adhesiveness to other materials.

Al₂O₃ has excellent electrical properties and chemical/electrical stability at high temperatures so it is a candidate substrate material for high temperature operation. In comparison with Al₂O₃, AlN has a higher thermal conductivity and a lower CTE which is close to that of SiC, so it is a good substrate material for packaging SiC high temperature and high power devices. The CTEs of a and b polycrystalline SiC are very close to that of single crystal SiC, so thermal-mechanically they are ideal substrates for packaging large SiC die for operating in a wide temperature range. However, both the dielectric constants and the dissipation factors of these materials are relatively high [4]. In order to be used as a packaging substrate, the surface properties of polycrystalline SiC must be modified. After appropriate surface modification these materials might still be suitable only for low frequency application because of their high dissipation factors. Based on these discussions, AlN and 96% Al₂O₃ were selected as high temperature substrate materials.

Metallization/Electrical Interconnection System: Most metals and alloys oxidize at temperatures near 500^oC in air. So the metals and alloys commonly used in conventional IC packaging such as copper, aluminum, and gold/nickel coated Kovar are excluded from packaging applications at temperatures of 500^oC and above unless a perfectly hermetically sealed inert/vacuum environment is available. At temperatures above 200^oC, intermetallic phases form at the interface of metals, such as Al and Cu. An intermetallic phase very often reduces the mechanical strength of the interconnection system. Thus, achieving material consistency in an interconnection system becomes extremely important in order to avoid thermal mechanical failure at high temperatures.

Precious metals are naturally considered for substrate metallization and electrical interconnection materials because of their chemical stability and good electrical conductivity. But some precious metals, such as platinum (Pt) and palladium (Pd) react with atomic hydrogen (H) to form H rich alloy at elevated temperatures. Though this is desirable for gas sensing devices [5], it is not so for electrical interconnection applications, because the phase transition may cause significant changes in the physical and electrical properties of these metals. Gold (Au) is extensively used for both substrate metallization and thin wire-bond in packaging and hybridizing conventional ICs. Besides the high conductivities and superior chemical stability at high temperatures, Au also has a low Young’s modulus and a narrow elastic region. As it will be discussed in the Conductive Die-attach section, these features of Au are helpful to reduce thermal stress generated at the Au/die and the Au/substrate interfaces due to CTE mismatches if Au thick-film material is used as die-attaching interlayer. These features of Au are especially important to packaging high temperature MEMS because a wide range of operation temperature is of concern and the thermal mechanical stress is critical to the reliability of the packaged device. It has been reported that Au thin film/wire with small grain size suffered from electro-migration of Au atoms at grain boundaries at high temperature under extreme current density (~10⁶ A/cm²) operation [6]. Surface modification and coating were suggested for Au conductor in order to be able to operate at high temperature and high current density [6].

Conductive Die-attach: Generally, die-attach materials are expected to be electrically and thermally conductive and physically/chemically stable at high temperatures, and to permit a die attaching process at a temperature within the temperature range of device operation. For applications in high temperature MEMS packaging, the thermal mechanical properties of die-attach material such as CTE, Young’s modulus, fatigue/creep properties, and their temperature dependencies are very much of concern since the die attaching material is in intimate contact, both electrically and mechanically, with the die and the substrate. The die attaching material is, therefore, also expected to thermo-mechanically compensate for any possible CTE mismatch between the die and the substrate materials. Another major concern of die-attaching materials for high temperature application is long-term chemical and mechanical stabilities of its interfaces formed with the die and substrate materials at high temperatures. If the die-attach is expected to be electrically conductive, the electronic properties of its interface with the die would also become critically important. Combining all these mechanical, chemical, and electrical requirements, it is apparent that a material system for die-attach with a suitable attaching process is critical to the success in packaging high temperature MEMS device.

The thermal mechanical stress of the die-attach due to the mismatches of CTEs of the die, the attaching material, and the substrate may cause degradation and failure of packaged devices. The extreme case of die-attach failure caused by thermal mechanical stress is cracking of the die or the attaching material. For high temperature MEMS devices, besides the failure due to fatigue and creep in the die and attaching materials, thermal stress can also cause undesired device thermal response, irreproducibility of device operation, and output signal drift. Therefore, the thermal mechanical failures of the die-attach due to material CTE mismatches are expected to be common and important thermal mechanical issues which need to be addressed in packaging MEMS devices, especially high temperature MEMS devices.

As discussed in the last section, 96% Al₂O₃ and AlN are selected for substrate materials because of their high temperature chemical and electrical stabilities. Au thick-films provide basic chemical and electrical stabilities at high temperatures [7,8], therefore are selected for metallization and wirebond. In this section we discuss an Au thick-film based 500^oC operable electrical interconnection system for packaging low power high temperature microsystems.

Au thick-film was screen-printed on a ceramic substrate (AlN or 96% Al₂O₃) and cured at 850^oC in air using the recommended curing process [9], to form printed wire and metallization pads for wire-bond. In order to examine the high temperature stability of the printed thick-film circuit, the test circuit was electrically tested at 500^oC in air for a total of ~1500 hours using four probe resistance measurement. The electrical resistance of the thick-film wire/circuit was first measured at room temperature, then the temperature was ramped up to 500^oC for ~1000 hours without electrical current flow and the resistance of the wire was measured periodically. The resistance fluctuated slightly within 0.1% during the first 1000 hours test, as shown in Figure 1. After testing for 1000 hours without electrical bias, the circuit was biased with 50 mA DC current and the resistance was continuously monitored. The resistance fluctuated slightly within 0.1% for 500 hours with electrical bias. This very small change in resistance is acceptable for almost all envisioned high temperature device packaging applications.

Figure 1: Normalized resistance of thick-film wire at various temperatures with and without DC	Figure 2: Normalized resistances of wire-bond test circuit measured at room temperature and 500°C vs. test time at 500° C with and without DC bias.

In addition to the high temperature electrical validation discussed above, the Au thick-film metallization system needs to be mechanically evaluated at high temperatures in order to be reliably applicable at elevated temperatures. The tensile strength of Au thick-film metallization on 96% Al₂O₃ substrate has been tested at room temperature after extended storage at 500^oC [7,10]. In order to examine the mechanical strength and the thermal dynamic stability of the binding system of Au thick-films at high temperature, the shear strength of Au thick-film metallization on 96% Al₂O₃ substrate was tested at temperatures up to 500^oC. The shear strength (breaking point) at 500^oC reduced by a factor of ~ 0.80 with respect to that at 350^oC while the shear strength (breaking point) at 350^oC was close to that at room temperature. The shear strength of Au thick-film designed for AlN were not as high as those for Al₂O₃, but it was sufficient for application in microsystem packaging operable at 500^oC.

Figure 3: Schematic diagram of as - fabricated SiC device and die-attach structure.

After the electrical and mechanical qualifications of Au thick-film metallization on Al₂O₃ and AlN substrates, the electrical stability of thick-film metallization based wire-bond test circuit [9] including thick-film conductive wire/pads, bonded thin Au wires, and the interfaces between them were extensively tested at high temperature with and without electrical bias in oxidizing air. The test sample is composed of 22 units of 1 mil Au wire-bond (44 bonds) in series. The resistance of the wire-bond sample was measured at room temperature and 500^oC at various testing times at 500^oC. The resistance was first measured at room temperature, followed by ramping the temperature up to 500^oC and the resistance was monitored in air without electrical bias for 670 hours. As shown in Figure 2, the temperature was then lowered back to room temperature and the resistance was recorded again. After this thermal cycle, the circuit resistance was continuously monitored for a total of 1200 hours at 500^oC in air without electrical bias (current flow), followed by another 500 hours at 500^oC with 50 mA (DC) current. The resistances under all these conditions were desirably low (less than 0.5 W per unit) and decreased slowly and slightly at an average rate of 2.7% over the 1500 hour testing period. The rate of resistance decrease under the DC bias is close to that without electrical bias.

An identical wire-bond circuit of that tested in static thermal environments was electrically tested in dynamic thermal environment. The wire-bond circuit was tested under thermal cycles between room temperature and 500^oC with an initial temperature rate of 32^oC/min for 123 cycles first, then at the temperature rate of 53^oC/min (higher than thermal shock rate) for additional 100 cycles with 50 mA electrical bias. The maximum change in electrical resistance during the thermal cycles is 1.5% at room temperature, and 2.6% at 500^oC [11].

An Au/Ti/SiC Schottky diode with a Ni ohmic contact on the backside was used as a device to test the die-attach scheme developed for high temperature operation [12]. After dicing, the 1 mm x 1 mm SiC diode chip was attached to a ceramic substrate (either AlN or 96% Al₂O₃) using Au thick-film material as shown in Figure 3. This Au thick-film die-attaching scheme resulted in a low resistance die-attach which is necessary for packaging many devices with vertical topologies.

The optimum process for attaching SiC dies (with Ni contact) to the ceramic substrate was investigated. The thick-film uniformity issue needs to be addressed first. As discussed elsewhere [12], the organic vehicle of "raw" thick-film materials evaporates during the initial drying process. Since the thick-film material is sandwiched by the ceramic substrate and the SiC die, the escaping organic vehicle molecules have a relatively long way to migrate to escape from the sides. During rapid drying this may distort somewhat the thick-film distribution, therefore, cause non-uniform thick-film distribution between the die and the substrate. A slower drying process (120^oC – 150^oC) was critical to keep the thick-film bonding layer uniform and the die parallel to the substrate after the curing process. It was also necessary to consider reducing the amount of organic vehicle evaporated during die-attach processing. A two-step die-attach process was used. A thick-film layer was first screen-printed on the substrate and cured at 850^oC, the SiC die was then attached to the cured thick-film pattern with minimal amount of subsequent thick-film.

Figure 4, Scanning Electron Microscope (SEM) micrograph of thick film surfaces cured at (a) 500oC for 25 min, (b) 600oC for 20 min, and (c) 850oC for 15 min. (a) Micro powder structure indicating insufficient boundary diffusion. (b) Chain structure replaces powder structure indicating a critical curing condition. (c) A large and smooth grain structure indicating solid film formation.

Figure 5: I-V curve of attached SiC test-diode characterized at 500 oC after being tested for 1000 hours at 500 oC oxidizing air.	Figure 6: Minimum specific dynamic resistance (normalized to device area) calculated from I-V data vs. heating time at 500 oC. This resistance includes resistances contributed from the Au(Ti)/ SiC rectifying interface, SiC wafer, the die-attach materials/ interfaces. Resistances of the bonded wire and the test leads have been subtracted.

The attached SiC test diode (Figure 3) was characterized by current - voltage (I-V) measurements at both room temperature and 500^oC for various heating times. A minimum dynamic resistance (dV/dI) in a high current (forward biased) region of the I-V curve was used to estimate both the stability and the upper limit of resistance of the die-attach structure (both interfaces and materials), as shown in Figure 5. This dynamic resistance includes forward dynamic resistance of Au/Ti/SiC interface, SiC wafer bulk resistance, the die-attach materials/ interfaces resistance, bonded wire resistance, and the test leads resistance in series. The resistance contributed from test leads and bonded wire were measured independently and subtracted. The attached device was first characterized by I-V measurements at room temperature. The device exhibited rectifying behavior and the minimum dynamic resistance after subtracting test-leads/bond-wire resistance (applies to all the following discussion) measured under forward bias was ~ 2.6 W , as shown in Figure 7. The temperature was then ramped up to 500^oC (in air) and the diode was in situ characterized periodically by I-V measurement for ~1000 hours. During the first 70 hours at 500^oC the (lowest) dynamic resistance under forward bias increased slightly from 3.3 W to 3.8 W . After that the dynamic resistance decreased slightly and remained at an average of 3.1 W . The diode was then cooled down to room temperature and characterized again. The minimum forward dynamic resistance measured at room temperature was 3.3 W . It is worth noting that the device's I-V curve changed somewhat with time during heat treatment at 500^oC. However, the dynamic resistance of attached diode remained comparatively low over the entire duration of the test and temperature range, indicating a low and relatively stable die-attach resistance.

Table 1: Basic material properties of SiC, Au, 96% alumina, and AlN used for FEA simulation for die-attach structure.

As it was discussed in Material Requirements section, the mechanical issues of most concern for high temperature MEMS packaging are the die-attach thermal stress problem and the general guidelines for material selection, structure design, and optimization of attaching process to minimize overall thermal stress of the die-attach structure. Assuming that a conventional die-attach structure, in which the die-backside is attached to a substrate using an attaching material layer, is adopted, the typical die-attach structure is illustrated in Figure 3. The die-attach using Au thick-film material discussed in last section is a typical example of this structure.

For high temperature microsystem packaging, thermal mechanical properties of the die-attach structure need to be addressed at two levels: 1) Mechanical damage of the die-attach

structure resulting from thermal mechanical stress. 2) Thermal stress/strain effects on the mechanical operation of devices. The failures at both levels are rooted in thermal mechanical stress of the die-attach. The thermal mechanical governing equations [13] of the die-attach are complicated, but analytically solvable in some cases [14,15]. References 14-15 have investigated the design of the die attach assembly using closed analytical solution assuming linear elastic material properties. Nonlinear effects were also considered in a simplified model in reference 15. Considering the wide temperature range and low yield strength of gold thick-film, a non-linear elastic-plastic finite element analysis (FEA) was used to simulate Au thick-film based SiC die-attach as an example of die-attach optimization for packaging high temperature MEMS.

The basic mechanical properties of SiC, Au, AlN, and 96% Al₂O₃ and their temperature dependence used for FEA simulation are listed in Table 1 [11]. The temperature dependence of Young’s modulus of AlN in a wide temperature range has not been reported, so it was extrapolated as a constant from the data at room temperature. Poisson’s ratios of both single crystal 4H-SiC and AlN are not published, so they were estimated according to those of other carbides and nitrides. The thermal and mechanical properties of 4H SiC were assumed isotropic. Since the yield strength of Au thick-film material has not been published, the simulation was conducted in a range of yield strength from 650 to 3000 psi. The numerical calculation using the yield strength at the low end diverged.

Figure 7: Thermal stress and strain distribution in SiC die and Au thick-film layer at room temperature, the relaxing temperature is 600oC. (a) Von-Mises stress distribution in SiC die. (b) Maximum Principal Stress distribution in SiC die. (c) Equivalent Plastic Strain in Au thick-film layer.

Figure 7(a) and (b) show Von-Mises stress and Maximum Principal Stress contours of a quarter of SiC/Au/AlN die-attach structure at room temperature with relaxing temperature of 600^oC. Horizontally, at the interface with a Au thick-film layer, the stress in the die basically increases with the distance from the center of the die attach interface, the stress reaches a maximum at the area close to the die edges, especially, at the corner. This is understandable. The source of thermal stress of the die-attach structure is CTE mismatch at bonding interfaces. At the area far from the neutral point (larger distance from neutral point, DNP) the trends of relative displacement with respect to Au thick-film, driven by the CTE mismatch, would be larger. From this it can be predicted that the maximum thermal stress would increase tremendously with increase of the die-size, or attaching area. Vertically, the stress attenuates rapidly with the distance from the interface. At the die center region the stress near die surface attenuates by a factor of 1/80 with respect to the stress at the interface. With this picture of thermal stress distribution one can conclude that flip-chip bonding would not be recommended for high temperature MEMS devices if the CTE mismatch is not well controlled, and a thicker die (or a stress buffer layer of the same material) can significantly reduce the thermal stress at die surface region.

In comparison with AlN substrate, 96% Al₂O₃ substrates have relatively higher CTEs (~6.2^oC compare with ~3.9^oC of AlN). The FEA results indicate that using AlN substrate would result in an improvement of maximum Von-Mises stress in SiC die by a factor of 0.29, an improvement of Von-Mises stress in the substrate by a factor of 0.33, and an improvement of MPS in Au thick-film layer by a factor of 0.42. This improvement of thermal stress/strain corresponds to an improvement of fatigue lifetime of Au thick-film layer by a factor of 4.3 – 9.0 (assuming the power law exponent in Coffin-Mason model, C, is -0.4 and -0.6, respectively). So in terms of thermal mechanical reliability of die-attach, AlN is suggested for packaging SiC high temperature MEMS devices compared to 96% Al₂O₃ owing to the fact that the CTE of AlN is close to that of SiC.

Figure 8 shows maximum Von-Mises Stress in substrate and SiC and the EPS of the thick-film layer vs. the thickness of Au attach layer. The maximum stress in the SiC die decreases by a factor of 0.75 with respect to the thickness change from 20 m m to 50 m m, for AlN substrate, while the maximum stress in the SiC die decreases by a factor of 0.5 with respect to the thickness change from 20 m m to 50 m m, for 96% Al₂O₃ substrate. The increase of Au layer thickness also significantly improves the stress in AlN substrate, as shown in Figure 8(b). Figure 8(c) shows the maximum EPS in Au layer vs. thickness of Au attaching layer. The increase of the thickness from 20 m m to 50 m m significantly reduces the EPS in the Au thick-film layer in both AlN and Al₂O₃ cases.

Besides the dependence of thermal mechanical configuration of the die-attach on material properties of the die, the attaching layer, and the substrate, the thermal mechanical stress in a die-attach structure also depends on the temperature deviation from the relaxing temperature, T_R, at which the structure is thermal-mechanically relaxed [13,16]. In order to assess the relaxing temperature effects on the thermal stress of the die-attach structure, the stress distribution of the die-attach at room temperature is simulated by FEA assuming that the structure is relaxed at various temperatures (from 300 - 600^oC). Figure 9 shows the maximum Von-Mises stress in the die and EPS in Au thick-film layer vs. the relaxing temperature. If the relaxing temperature could be lowered from 600^oC to 300^oC, the maximum Von-Mises Stress in the die can be reduced by a factor of 0.8. And the maximum EPS in Au thick-film layer can be reduced by a factor of 0.5. The fatigue lifetime corresponding to the stress reduction is improved by a factor of 3 (assuming the exponent in Coffin-Mason model of fatigue, C, is -0.6). Ideally, the thermal mechanical property of the die-attach structure is optimized if the relaxing temperature could be set at the middle of the operation temperature range.

Figure 8: Maximum stress and strain of die-attach vs. the thickness of Au thick-film interlayer, at room temperature. (a) von-Mises stress in AlN substrate, (b) von-Mises stress in SiC die, and (c) EPS in Au thick-film	Figure 9: Relaxing temperature dependence of maximum stress and strain in SiC chip, substrate, and Au attaching layer.

6. Summary and Discussion

Ceramic substrates, Al₂O₃ and AlN, and Au thick-film metallization based material system were discussed for low power high temperature chip level packaging. The electrical interconnection system of this packaging system has been extensively tested in a temperature range from room temperature to 500^oC with and without electrical bias in oxidizing environments. The mechanical strengths of Au thick-film metallization on both Al₂O₃ and AlN substrates have been preliminary tested at 500°C. Following electrical and mechanical tests in static thermal environments, the Au thick-film wire-bonds were evaluated in extremely dynamic thermal environments from room temperature to 500°C. The test sample including 44 Au wire-bonds, survived 120 thermal cycles at temperature rate of 32°C/min and 100 additional cycles at 53°C/min in oxidizing environment with 50 mA DC current which is sufficient for many low power devices. An attached SiC diode using this technology was successfully tested at 500°C in an oxidizing environment for more than 1000 hours setting lifetime records for high temperature electronic packaging.

In order to optimize the thermal mechanical properties of Au thick-film material based SiC die-attach, nonlinear FEA was used to simulate and compare the thermal mechanical stress/strain distributions against material, structure, and processing parameters to establish basic guidelines of material selection, structure design, and processing parameters determination.

The combination of versatile functions of MEMS devices and survivability/operability at high temperature introduces a new generation of micro-devices, high temperature MEMS, with revolutionary capabilities for many aerospace applications. Packaging these revolutionary devices, however, presents new challenges and research in device packaging. In meeting these challenges, innovative packaging materials possessing superior physical/chemical properties suitable for high temperature operation, innovative structure/design meeting these specific device and operation requirements, and innovative packaging processes able to accommodate both the new materials and the new structures are expected.

The authors would like to thank Dr. Jih-Fen Lei for all her advices and encouragement to write this paper. The authors are very grateful to Dr. Lawrence G. Matus for proofreading the manuscript. The high temperature electronic packaging research at NASA Glenn Research Center is currently supported by NASA Glennan Microsystems Initiative (GMI) and NASA Electronic Parts and Packaging (NEPP) program.

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