Background. In early 1995, the Jet Propulsion Laboratory formed a consortium to evaluate the quality and reliability of ball grid arrays (BGAs) and to help build the infrastructure for this technology. NASA Code Q, Office of Safety & Mission Assurance (OSMA) funded JPL and consortium team members furnished in-kind contributions by providing internal resources and expertise. The consortium accomplished a great deal and answered many technical issues raised during the start of the BGA program in 1995 (1). It was recognized that wider acceptance of BGA technology will afford NASA as well as industry consortium members inexpensive access to this technology and support miniaturization thrusts for their next generation applications. BGA is now becoming an acceptable alternative for high density applications.

MicroBGA packages and Surface Mount Chip Scale Package (SM CSP) technology with many characteristics of BGAs now are at the stage that BGAs were about three years ago. This technology is being investigated under the NASA's Advanced Interconnect Program (2).

MicroBGA Program. The microBGA program was funded to develop quality and high reliability for assembly technology. The microBGA program is considered to be a natural extension of the BGA program toward understanding technical issues associated with a greater level of miniaturization which will bring about a significant reduction in package size and weight. The two technologies involve very similar technical issues including the development of quality and reliability methodologies. A microBGA consortium is being formed which will include the current BGA team members and additional new members with expertise in this technology. This new consortium will address many challenging issues regarding the implementation of this technology. The microBGA consortium will concentrate its activities in the following areas as well as other aspects of the technology, identified by the team members:

• Defining and developing quality assurance methodologies required for low volume, high reliability manufacturing environments. These methodologies will also benefit larger production interests since they support the initial set up of any manufacturing.
• Defining the manufacturing processes such as the critical parameters involved with the manufacture of microBGA assemblies and mixed technology, including DCA, and identifying control parameters.
• Reliability performance of various microBGA packages and mixed technologies covering DCA used at JPL and those of interest to the other consortium members. The selected components will have I/O counts for near and longer term applications.
• Similarly to the BGA program, a Design of Experiment (DOE) will be used to toggle Printed Wiring Board (PWB) materials, packages, manufacturing process variables, and environmental conditions.
• Inspection techniques will be evaluated along with failure analysis on assembly failures. Analytical tools will be developed to fully assess assembly quality and reliability, and to project life for field applications.

MINIATURIZATION TRENDS IN SM PACKAGES

SMT - CSP and DCA. In surface mount technology (SMT), electronic packages are mounted and terminated directly onto the PWB surface rather than inserting the leads into plated through-holes (PTHs). Survey results from the Issues in Global Technology survey (Surface Mount Technology Magazine, October 1996 issue) indicate that the percentage of surface-mount chips is expected to increase in 1997 from 47.5 to 49.6, whereas through-hole technology use is expected to decline from 26.9 to 23.3.

There are several surface mount package styles, both active and passive. Active devices are divided into those with terminations of leads on the periphery of the component, two sides or four sides, or those with terminations (either pads or solder bumps) over much of the bottom of the component. Peripheral Array Packages (PAP) have less potential for significant reduction in size in conjunction with increase in I/O counts compared to Area Array Packages (AAPs). The BGAs from the latter category are becoming an acceptable alternative.

The CSP version of two sided PAP are the Lead-On-Chip (LOC) packages. Miniaturized package versions with four sides are the Slim Tape Chip Carriers. The CSP versions for PAP are micro- (or mini-)BGA packages generally with eutectic balls or Land Grid Arrays (LGA). The CSP packages similar to other packages will resolve incompatibility of IC's pad to assembly/reflow process as well as protection from physical damage.

Another level of miniaturization is accomplished by directly attaching the bare die on the PWB. The direct Flip Chip On Board (FCOB) is the ultimate miniaturization level achieving nearly 70% efficient use of the area of the die ratio to the PWB's foot print. In FCOB, solder bumps are permanently attached to the face of bare die, the flip side is mounted on the PWB. In Chip-On-Board, with about 50% use of area efficiency, wire bonded pads are used for second level wire bonding onto the PWB. In the Tape Carrier version, the second level bonding is accomplished using tapes.

CSPs. CSPs are packages that are up to 1.2 or 1.5 times larger than the perimeter or the area of the die, respectively. These packages are seen to be a vision of the future, since they provide the benefits of small size, performance of the bare die or flip chip with the advantage of standard die packages. CSP packaging accomplishes many purposes including the following:

• Providing solder balls and leads that are compatible with the PWB pads for reflow assembly processes, whereas aluminum pads are not compatible.
• Redistributing the tight pitch of the die to the pitch level that is within the norm of PWB fabrication. Small sizes of CSPs do not permit significant redistribution. Current cost effective PWB fabrication limits allow full adoption of the technology, especially for high I/O counts.
• Protecting the die from physical and alpha radiation (soft error) damages, and providing a vehicle for thermal dissipation and ease of testability for die functionality.

• Interposer packages with either flex or rigid substrate. The flex type employs flex circuit, e.g. Cu/polyimide structure and rigid type using rigid substrates, e.g. Bismaleimide Triazine (BT) resin. For example Tessera's microBGA package, a flex type, uses TAB-like interconnects (S shape for the maximum thermal mismatch absorption) with an elastomeric layer to translate the die pads to an SMT pitch and footprint. The elastomeric layer decouples the thermal expansion of the silicone chip (CTE 2-3 ppm/C) to that of the PWB (CTE for FR-4 ~15 ppm/C). An example of a CSP with a rigid substrate is Motorola's Slightly Larger than IC Carrier (SLICC) that employs FR-4 or BT substrate. The C4 (Controlled Collapse Chip Connection) flip chip die on BT substrate is redistributed through solder balls to the pitch acceptable for PWB assembly. The height of the latter packages are within 1-2 mm higher than the former which is in 0.8-1 mm range.
• Wafer level molding and assembly redistribution. The wafer level molded package is processed at the IC level using thin film metallization in the inter-die scribe area prior to wafer singulation. Currently, these very thin packages (0.3 to 0.5) are limited to peripheral I/O formats and they are easily converted to a three dimensional stacking version for memory cubes. The Sandia miniBGA is an example of a wafer assembled CSP where thin film metal/polymer redistributes the location of the solder bumps over the chip to make these compatible with the surface mount footprint. The height of the latter package type increases by the thickness of metal polymer layer from the former package and is between 0.5 to 0.7 mm.
• Lead On Chip (LOC) packages use a lead frame that extends over the top of the die rather than the periphery to enable the use of a standard plastic package.

Quality Assurance Challenges. Every space mission is unique and electronic boards are specially designed for specific missions. Space applications may range from shuttle missions lasting a few days to missions to outer solar systems requiring multi-decade service life. The difference in reliability requirements plays a key role in the selection/design and inspection/testing processes. Unlike commercial applications which measure reliability failures in parts per million, the acceptable risk for the success of a space mission is associated with the first failure of electronic parts or interconnection. Even though the highest reliability is demanded, it is extremely difficult to quantify the reliability level requirement and demonstrate its indices. One reason is due to the unavailability of solder joint field data and failure statistics. This limits the exact definition of reliability assurance. Assurance must depend on qualification testing methodologies unique to accelerated environments along with credible analytical prediction.

Until recently, a few critical space components were tailor-made parts, but the majority of components were selected from available parts lists based on military specifications. The current constraint on budgets and changes in military specifications along with the applications of bold new technologies for space missions necessitates the use of advanced commercial electronic packages. This is more critical in the miniaturization areas where even the PWB manufacturers are lagging behind the demand for rapid advancement in IC and package development. Use of advanced packages including BGAs and CSPs, specifically their plastic versions, are contingent upon resolution of many issues of space applications such as radiation damage. Another key environmental feature of space that must be considered is the thermal/vacuum environment. The absence of gas convection in a vacuum environment can drastically change the temperature control and design characteristics of the advanced electronic components with high dissipation powers.

Since only a very small production quantity is involved, critical manufacturing steps are severely limited. Often, NASA requires a coupon-certification of the manufacturing process from potential candidate manufacturers; however, there are generally not enough test boards to fine tune the fabrication processes to achieve the level of quality obtained in a commercial mass production line. As a result, 100 percent visual inspection often becomes mandatory to provide another quality assurance step. MicroBGAs, similarly to BGAs, with hidden solder balls, obsolete the use of visual techniques for quality assurance and therefore more advanced techniques are sought. In addition to the development of criteria for visual characterization of peripheral solder joints, other techniques including X-ray and Scanning Acoustic Microscopy need to be further developed for assuring the quality of solder joints.

CONCLUSIONS

Board level solder joint reliability information is critical to the acceptance of microBGAs as alternative packages. The very limited data available on cycles to failure of assembled packages are of even less value, since the data was generated under significantly different environmental conditions. For wider applications of this technology, the potential user will need reliability data for its design since often they have no resources, time, or ability to perform complex environmental characterizations. JPL is currently coordinating an industry-wide BGA consortium that successfully accomplished building and testing of nearly 400 test vehicles. Similarly to the BGA program, a consortium is being formed to address many assembly reliability issues. The objectives of the microBGA consortium are to address many technical issues regarding the interplay of package type, I/O counts, PWB materials, and manufacturing variables on quality and reliability of assembly packages

REFERENCES & ACKNOWLEDGMENTS

1. Ghaffarian, "CBGA/PBGA Quality & Reliability," Electronic Packaging Workshop for Space Applications, November 5-6, 1996, Pasadena, CA
2. Barela, "NASA's Advanced Interconnect Program (AIP)," Electronic Packaging Workshop for Space Applications, November 5-6, 1996, Pasadena, CA