In a conventional, bulk-Si microcircuits, the active elements are located in a thin surface layer (less than 0.5 m m of thickness) and are isolated from the silicon body with a depletion layer of a P-N junction. The leakage current of this P-N junction exponentially increases with temperature, and is responsible for several serious reliability problems. Excessive leakage currents and high power dissipation limits operation of the microcircuits at high temperatures. Parasitic n-p-n and p-n-p transistors formed in neighboring insulating tubs can cause latch-up failures and significantly degrade circuit performance.

Silicon-on-insulator (SOI) technology employs a thin layer of silicon (tens of nanometers) isolated from a silicon substrate by a relatively thick (hundreds of nanometers) layer of silicon oxide. The SOI technology dielectrically isolates components and in conjunction with the lateral isolation, reduces various parasitic circuit capacitances, and thus, eliminates the possibility of latch-up failures. Figure 1 shows schematic cross sections of the bulk-Si and SOI CMOS transistors.

SOI technology simplifies manufacturing process by eliminating well and field implantation steps and allows fabrication of smaller, denser, and faster microcircuits, with reduced interconnect cross-talk. These features make SOI technology particularly attractive in emerging system-on-chip microcircuits, micro-electromechanical systems (MEMS), and integrated optics applications. Dielectric isolation in SOI also helps in decoupling the analog and digital components in mixed-signal microcircuits by reducing the substrate cross-talk [1]. Another appealing aspect of SOI technology is its compatibility with the standard semiconductor fabrication.