A JPL-led chip scale package (CSP) Consortium of enterprises, composed of team members representing government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects.

The experience of the Consortium in building more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and the environmental test results has now been published as a chip scale package guidelines document and distributed by Interconnection Technology Research Institute (ITRI).

The Consortium assembled fifteen different packages from 48 to 784 I/Os and pitches from 0.5 to 1.27 mm on multilayer FR-4 printed wiring board (PWB). In addition, two other test vehicles built by two team members, each had a control wafer level CSP package for data comparison. Assemblies were subjected to numerous thermal cycling conditions including -55°C to 125°C. Cycles-to-failure (CTF) test results to 500 cycles for the control CSP assembly are presented. Also, CTF results of two fine pitch BGAs with 0.8 mm pitch and different die sizes for a test vehicle are compared. In addition, a number of test vehicles included a fine pitch ball grid array (BGA) interconnect structure at Radio Frequencies (RF) using a 50-Ohm transmission line and a resonant circuit. Return and insertion losses were determined and presented prior to and after 500 cycles and presented.