Background

Complementary heterostructure field effect transistor (CHFET) is an advanced GaAS based IC technology that offers up to 4x higher speed and 6x lower power dissipation than silicon based CMOS technology. The CHFET technology was developed by Honeywell SSEC for DOD applications and according to the manufacturer, additional features include CMOS like design flexibility with complementary N-channel and P-channel FETs), high switching speed (multi-GHz), wide operating temperature range (4° K to 400° C), and inherent radiation hardness. These features made the CHFET an attractive candidate for potential use by JPL X2000/Europa Oribter project. Honeywell SSEC provided JPL X2000 project with several wafer lots of CHFETs. In order to space qualify these CHFETs, DC/RF life testing was proposed by JPL as part of NEPP task requirements, where as GSFC was to focus on thermal cycling characterization of these devices. Several sample devices (chips in bare die form) were sent to GSFC for thermal cycling.