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Gate Disturbance Effects in Flash Memories
File Name: 06285_NEPP Flash final 06 mod.doc | Date Submitted: 05/13/08
 

File Size:
24656KB
Document Author
Doug Sheldon - Douglas.J.Sheldon@jpl.nasa.gov
Jet Propulsion Laboratory
Phone: 818 393-5113 | FAX: None On File
[Additional User Information]

Download "Gate Disturbance Effects in Flash Memories" (24656KB) Now.
 
Description:
 
Abstract:
This report summarizes the results of Gate Disturbance testing done a group of Flash memories. Both NOR and NAND types of Flash memories were tested. Flash memory is the defacto standard for non-volatile semiconductor chip data storage for the entire spectrum of consumer and industrial products. NASA spacecraft architectures are still exploring the use of flash memories. Use of flash memory in spacecraft electronics is much more limited however. This is because of a combination of reliability and radiation concerns. This report is designed to address one of the reliability concerns. This is the particular failure mode that some times occurs in flash memories, gate disturb failures. The work was performed under the sponsorship of the NASA Electronic Parts and Packaging Program.
 
Related Project(s):
 
Related Area(s) of Emphasis:
High Performance Processor and Memory Technologies
Advanced and Emerging Technologies

 
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