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Task Plan - 08-108-1 CMOS Harmonic Oscillator Evaluation
File Name: Par-5a. Whittington - FY08 NEPP CMOS Harmonic Oscillator Evaluation Quad2.ppt | Date Submitted: 06/10/08
 

File Size:
82KB
Document Author
Doug Sheldon - Douglas.J.Sheldon@jpl.nasa.gov
Jet Propulsion Laboratory
Phone: 818 393-5113 | FAX: None On File
[Additional User Information]

Download "Task Plan - 08-108-1 CMOS Harmonic Oscillator Evaluation" (82KB) Now.
 
Description:
 
Abstract:
Highly accurate frequency generators are now available as completely integrated, single silicon chip CMOS circuits. These frequency generators are used as harmonic oscillators that can replace current quartz based crystals and related oscillators. Implementing this capability in an all silicon chip design provide: A. More stable frequency reference for serial interfaces when compared to quartz crystals, particularly over temperature. B. Minimizing bit error rates and support for higher reference frequencies. C. Significant improvement in phase noise and jitter. D. Increased mechanical robustness and reliability. These devices will be evaluated for latch-up sensitivity and long term reliability and stability over extended environmental conditions. Their performance to a QML-Q level qualification will be conducted. All NASA missions can benefit from this new technology by providing more robust and higher performance devices.
 
Related Project(s):
EPAR (Electronic Parts)
 
Related Area(s) of Emphasis:
Advanced and Emerging Technologies

 
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