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Preliminary Test Plan for Evaluating the Reliability of Cu-Based Metallization Systems
File Name: CuInterconnect_FSRAMTestPlan.pdf | Date Submitted: 09/14/01
 

File Size:
166KB
Document Author
Ashok Sharma - asharma@pop300.gsfc.nasa.gov
Goddard Space Flight Center
Phone: 301 286-6165 | FAX: 301 286-1695
[Additional User Information]

Download "Preliminary Test Plan for Evaluating the Reliability of Cu-Based Metallization Systems" (166KB) Now.
 
Description:
 
Abstract:

The advantages of using copper for interconnection in microcircuits are mostly due to its lower resistance (bulk resistivity) compared to aluminum metallization. Copper-based metallization has specific resistance of less than 2 m W -cm compared to more than 3 m W -cm for aluminum metallization. In combination with a reduced susceptibility to electromigration failures, this low resistivity property enables designing of highly scaled devices with significantly higher performance and reduced RC time delays. These features are mostly beneficial for devices such as high-performance microprocessors and fast static RAMs (FSRAM).

In addition to higher performance, the dual damascene technology incorporating copper interconnect processes, can potentially reduce the manufacturing cost by eliminating some of the labor intensive aluminum etching process steps. This makes copper interconnect technology quite attractive and is listed in the International Technology Roadmap for Semiconductors as the standard interconnect process for most submicron ULSI generation microcircuits and systems-on-chip (SOC) designs in the future.

 
Related Project(s):
EPAR (Electronic Parts)
 
Related Area(s) of Emphasis:
Advanced Interconnect Reliability

 
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