Abstract:
NAND Flash devices continue to increase in density. 8Gb devices are presently available. Current and future generations of NAND flash take advantage of multiple bits per cell. There are designs for both 2 bits/cell and 4 bits/cell. This increase in density is obtained as a tradeoff of performance, particularly Program endurance. NAND flash devices are also shipped with a certain percentage of known bad cells.
This combination of performance trade offs with known bad cells means that error correction software is critical to the accurate and reliable use of Flash memories for non-volatile storage. Modern error correction software is focused on wear leveling and spare sector algorithms. The effectiveness of such methods in the error correction needs to be verified to ensure candidate parts will meet NASA requirements.
This task will examine flash device reliability (endurance, disturb, retention, etc.) with and without error correction. The results will be used to enable reliable system design and architecture.
Related Project(s):
EPAR (Electronic Parts)
Related Area(s) of Emphasis:
High Performance Processor and Memory Technologies
Advanced and Emerging Technologies
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