Abstract:
This paper reviews many factors that affect interconnect reliability of commercial-off-the-shelf (COTS) chip scale package (CSP) assemblies. These include: package type, package build, voard design, and assembly variables. Methods of accelerated environmental testing were discussed and reasons for unrealistic life projections for CSP assembly reliability by numerous modelers is also examined. Prelinimary thermal cycling test results in the rance of -30°C to 100°C for test cehicles, especially a double sided assembly were also presented. It was concluded that availibility of meaningful assembly reliabiity test results are needed to accelerate implementation of this technology. The JPL-led CSP consortia are addressing many of these issues.
Related Project(s):
EPAC (Electronic Packaging)
Related Area(s) of Emphasis:
High Density Packaging Technologies
Advanced Interconnect Reliability