The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. Last year (1), team members reported their experience on technology implementation challenges, including design and build of both standard and microvia boards, assembly of two types of test vehicles, and preliminary aging and thermal cycling test results on trial test vehicles. Since then, more than 150 test vehicles, single- and double-sided, have been assembled and are presently being subjected to various environmental tests. This paper presents the experience of three consortium team companies on characterizing reliability behavior under four different thermal cycling environments. Lessons learned on assembly are given in a paper included in this proceedings.