Chip Scale Packages (CSP) are now widely used for many electronic applications including portable and telecommunication products. The CSP definition has evolved as the technology has matured and refers to those packages with a pitch of 0.8 mm and lower. Packages with fine pitches, especially those with less than 0.8 mm, and high I/Os may require the use of a microvia printed wiring board (PWB) which is costly and they may perform poorly when they are assembled onto boards. A test vehicle (TV-1) with eleven package types and pitches was built and tested by the JPL MicrotypeBGA Consortium during 1997 to 1999. Lessons learned by the team were published as a guidelines document for industry use[1].

The finer pitch CSP packages that recently became available were included in the next test vehicle of the JPL CSP Consortium[2]. The Consortium team jointly concentrated their efforts on building the second test vehicle (TV-2) with fifteen (15) packages of low to high I/O counts (48 to 784) and pitches of 0.5 mm to 1.27 mm. In addition to the TV-2 test vehicle, other test vehicles were designed and built by individual team members to meet their needs. At least one common package was included as control in each of these test vehicles in order to be able to compare the environmental test results and understand the effects of PWB build and manufacturing variables.

One test vehicle was designed and assembled by Hughes Network Systems using their internal resources and is identified as TV-H. This paper presents the most recent thermal cycling test results to 900 cycles which are currently being performed under -55 to 125°C conditions for packages with various die sizes. Mechanical fatigue test results for the 280 I/O count packages under various deflections with and without local heating are also presented.