The JPL-led CSP Consortium of enterprises representing government agencies and private companies has joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. Since last year, more than 150 test vehicles, single- and double-sided, have been assembled and are presently being subjected to various environmental tests. As an active participant in the consortium, Celestica has been heavily involved in test vehicles design review and test vehicle assembly. Its Customer Oriented Rapid Engineering Lab (CORE Lab) was used for assembly and inspection of the CSP test vehicles. Key objective was to integrate CSPs into main stream surface mount technology (SMT) assembly.

In this paper, the assembly process flow, solder paste for different stencil design, manufacturing defects, X-ray inspection results, and ultrasonic characterizations are reported. Optimize process techniques which were learned during the six month assembly of test vehicles are also presented. Also, manufacturing robustness of CSPs were investigated by increasing the placement offset during assembly. Limiting offsets for different CSPs were reported and finally, future activities on assembly process optimization and characterizations were reviewed.

Keywords: electronic assembly, SMT, CSP, fine pitch, microvia technology, BGA