Abstract:
Reliability evaluation was performed on three types of power FET transistors encapsulated in TO220 and SOT223-style plastic packages. These parts were subjected to solder reflow simulation per JEDEC JESD22-A113 standard and to environmental stress testing, including biased HAST at 85% RH and temperatures from 110 to 150 oC, and various temperature cycling (up to 1000 TC from –55 oC to 125 oC, 300 TC from 0 oC to 180 oC, and 300 cycles from 20 oC to 200 oC). Electrical measurements and C-SAM mode acoustic examinations were performed after each of the stress testing.
Evolution of delaminations at critical wire bond and top-of-the-die areas, electrical characteristics of the parts, and failures during stress testing have been analyzed. The analysis indicates that preconditioning, and in particular, flux application, has a significant effect on results of reliability testing. The effectiveness of CSAM examination for screening out potential failures is discussed.
Parts after HAST manifested extensive delaminations at the die-molding compound interface and had several sites of corrosion on the surface of aluminum metallization. However, many of the HAST failures were due to the charge-induced degradation of the transistors. Reproducibility of HAST, possible reasons for development of moisture-induced delaminations, their role for reliability testing, and a mechanism of the charge-induced degradation during HAST are discussed.
Related Project(s):
EPAC (Electronic Packaging)
EPAR (Electronic Parts)
Related Area(s) of Emphasis:
Newly Available Technologies and COTS
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