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Preliminary Reliability Evaluation of Copper-Interconnect Metallization Technology
File Name: CuInterconnect_Evalreport.pdf | Date Submitted: 09/14/01
 

File Size:
2537KB
Document Author
Ashok Sharma - asharma@pop300.gsfc.nasa.gov
Goddard Space Flight Center
Phone: 301 286-6165 | FAX: 301 286-1695
[Additional User Information]

Download "Preliminary Reliability Evaluation of Copper-Interconnect Metallization Technology" (2537KB) Now.
 
Description:
 
Abstract:

The advantages of using copper for interconnection in microcircuits are mostly due to its lower resistance compared to the aluminum metallization. Copper-based metallization has specific resistance of less than 2 m W -cm compared to more than 3 m W -cm for aluminum metallization. In combination with a reduced susceptibility to electromigration failures, this enables designing of highly scaled devices with significantly reduced time delays. These features are mostly beneficial for high-performance microprocessors and fast static RAMs (FSRAM).

In addition, copper interconnect process uses the dual damascene technology for deposition of copper, which can potentially reduce the manufacturing cost by eliminating some labor intensive steps of aluminum etching. This makes copper interconnect use quite attractive for semiconductor industry, and positions this technology as a standard interconnect process for the most high performance microcircuits in the future.

Major problems with copper metallization are due to some specific physical/electrochemical properties. Copper does not create a passive oxide film (as aluminum does), has poor adhesion and high rate of diffusion through silicon and dielectric layers (organic and inorganic). This introduces new failure mechanisms such as poisoning of the P-N junctions, charge instability and formation of resistive shorts caused by copper electrochemical migration.

The first on the market, copper-based FSRAM was manufactured by Motorola (the part is available since 1999). This part was used to gain experience with the copper-based interconnect design and technology, to analyze problems related to their evaluation and to obtain preliminary results of destructive physical analysis (DPA) of the parts.

Due to constraints caused by relocation of the GSFC Parts Analysis Lab, cross-sectional analysis of the part was performed by the Chipworks, Inc., Ottawa, ON, Canada [1].

 
Related Project(s):
EPAR (Electronic Parts)
 
Related Area(s) of Emphasis:
Advanced Interconnect Reliability

 
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