To date, surface-mount packages, whether J-lead or gull wing, have been key enablers in the drive to reduce the overall size of electronic systems and devices. Despite the maturity of this technology however, increasing pressure to enhance reliability, increase functionality, and reduce size while lowering costs has kept researchers and designers permanently at the drawing board.

The current answers to these challenges are surface-mount (SMT), package options that can be loosely divided into two groups: ball-grid arrays (BGAs) and chip-scale packages (CSPs). While both of these technologies have been around for a number of years, their relatively high cost has relegated them to only the most space-constrained applications. Now, the pressure many designers face to reduce system dimensions has brought about a gradual migration toward these newer packages.

Unfortunately, other major obstacles to the adoption of these technologies still exist. The very nature of these packages means that reliability is questionable and that conventional testing and rework methods no longer apply. Also, the competitive nature of the high-end IC business is such that many package/IC houses are loathe to divulge the exact failure rates of their package design. As a result, mistakes will be repeated, thereby slowing progress. In addition, the plethora of package options causes some confusion for designers who must choose from among them. Their decision is further hampered by the limited time they have to perform extended reliability and performance testing, thanks to ever-present time-to-market pressure.

As a result of all this, the Jet Propulsion Laboratory (JPL), Pasadena, Calif., undertook the task of performing extended, independent, performance and reliability testing of SMT packages, using the two categories outlined above (regular SMT BGAs and CSPs). Working for NASA, JPL is one of the few facilities that can independently test the devices over a long period of time without time-to-market pressures. While still a work-in-progress, test results are available, along with information on lessons learned from the design, manufacturing, inspection, and reliability of these assemblies.

A review of the board-level reliability of CSP assembly and the projected values for specific environmental conditions were extracted from the data. These findings offer valuable information on package robustness, and provide a better understanding of the challenges associated with the implementation of SMT technology, particularly with the new, advanced, miniature CSPs.