The previous report entitled, "Reliability Evaluation of Fully Depleted SOI (FDSOI) Technology for Space Applications," posted on the NEPP web site, provided a general overview of SOI technology including materials, process, reliability issues, and MIT/LL FDSOI processes and associated reliability test structures. The hot carrier degradation effects in the MIL/LL FDSOI FETs at V_g = V_d/2 conditions, which are known to maximize the interface trap generation have been investigated at JPL [1].

This report (Part II) of the continuing evaluation, addresses characterization of the N- and P-channel transistors, including scaling effects and estimation of the reproducibility of the front- and back-channel parameters was performed. The transistor measurements included threshold voltage, subthreshold slope, mobility of charge carriers, gate leakage currents, and investigation of the edge effects. Radiation effects and charge instability in FD SOIFETs will be discussed in part III of the report.