A JPL-led CSP Consortium of enterprises, composed of government agencies and private companies, recently joined together to pool in-kind resources for developing the quality and reliability of chip scale packages (CSPs) for a variety of projects. The Consortium’s experience of the build of more than 150 test vehicle assemblies, single- and double-sided multilayer PWBs, and environmental test results is now published as a chip scale package guidelines document and is being distributed by Interconnection Technology Research Institute (ITRI).

Assembly of the second test vehicle with 15 packages is currently underway. As part of the assembly, an in depth study on solder paste print quality for mixed CSP and BGA packages was performed at two facilities, Celestica and Storage Technology. A series of experiments was performed to establish solder paste deposition with screen printing process variables. A 3D laser measuring system in conjunction with reference copper traces was used to automatically measure solder paste volume. The quality of print was established by visual inspection. This paper presents the effects of screen printing parameters including stencil thickness, aspect ratio, squeegee length, squeegee materials, and pressurized print head on solder paste volume for packages with pitches from 0.5 mm to 1.27 mm and I/Os from 48 to 784.