Abstract:
One of the greatest tasks of packaging is connecting large passive devices, for example surface mount capacitors, with the active circuit elements, which are often all together as one or a few IC’s. With embedded passives, fabricated on silicon or other substrates using thin film technology, the portion of the circuit containing these traditionally discrete elements can be created all together, in batch, and eliminate the tedious picking, placing, and soldering process and these vulnerable joint. They also promise great savings in circuit volume, as well as potentially decreased parasitics and increased robustness. These devices are intrinsically low height, but circuit footprint could be drastically reduced by stacking passives within a substrate and by putting active die over them. In principle the process for making thin film passives can simply be repeated to stack devices. However, these steps must be demonstrated, and the interactions between nearby devices must be understood. While bump-bonding to attach die to properly metallized surfaces is commonplace, the impact of the thermal conditions for die attach procedures on the underlying materials must be assessed. Under the Center for Integrated Space Microsystems’ System on a Chip program Integral Wave Technologies, Inc. (IWT) fabricated eight “PASM Phase I” wafers to investigate these issues. The test vehicle includes stacked capacitors and resistors and metallization for the attachment of standard “daisy-chain” die. The data from these will lay the foundation for design rules for embedded capacitors and resistors. The Laboratory for Electronic Assembly and Packaging (LEAP) at Auburn University will conduct studies in die attachment, particularly the role of underfills, in addition to the tests by the advanced packaging group at JPL. Later in the year this NEPP task will subject these test structures to environmental stress.
Related Project(s):
EPAC (Electronic Packaging)
Related Area(s) of Emphasis:
Substrates and Embedded Passives Technologies
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