Implement the agreed task plan with consortia to create quantifiable board level assembly data correlation between manufacturing variables to interconnection reliability. Inspection criteria and processes will be developed and validated by testing to failure under various environments (thermal and dynamic). Failure modes will be identified and crack initiation and propagation as a function of material, part and location will mapped and guidelines will be provided.

Results will provide quantifiable data on time to failure for various packages, boards, and processes. Through continued teaming with the NMP, APEX, CISM, X-2000 development at JPL as well as involvement of NASA projects who have the desire to use Chip Scale technology, assist in the implementation CSP technology specially tailored for space application. Results will be disseminated by publishing a detailed, proven CSP manufacturing processes methodologies. Results will also be used in joint IPC/ITRI guidelines document with NASA.