Recent industrial trends show that new Thin-Small-Outline-Plastic (TSOP) devices are made with very thin molding compound and with a relatively large silicon chip.  However, when the molding compound gets thinner and the chip gets relatively larger, dynamic stresses on the silicon chip are expected to be different from those of the regular devices where the chip size is relatively small.  As all NASA sppaceborne PCB assemblies willl have to go through stringent randon vibration testing, understanding the dynamic stress distribution on large chips in TSOP packages will give us a good insight when selecting ultra-thin TSOP devices for electronic systems operating in severe dynamic environments.  This study uses TOSHIBA's 50 lead TSOP II 50-P-400 device (64 Mb synchronous DRAM0 as the baseline for numerical modeling.