A key issue yet to be fully addressed in chip-scale packaging is the matter of interconnection reliability. The main objective of the JPL-led CSP consortium, which included representatives from government agencies and private companies, was understanding quality and assembly reliability issues associated with the implementation of CSPs.

Our experience with implementing CSP technology challenges include design and fabrication of standard and microvia-based boards, as well as the assembly of two types of test vehicles. We will also discuss preliminary thermal cycling test results under four environmental conditions.

Finally, we will compare thermal cycling test results for single- and double-sided assemblies to the limited data available in the literature.