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Chip-Scale Package Reliability-Has it Been Proven?
File Name: rg-chip-scale.pdf | Date Submitted: 09/25/01
 

File Size:
63KB
Document Author
Reza Ghaffarian - Reza.Ghaffarian@jpl.nasa.gov
Jet Propulsion Laboratory
Phone: 818 354-2059 | FAX: 818 393-5245
[Additional User Information]

Download "Chip-Scale Package Reliability-Has it Been Proven?" (63KB) Now.
 
Description:
 
Abstract:

You may have seen summaries from the publication of a NEMI Roadmap earlier this year. You might have wondered, coincidentally, how these diminutive chip scale packages are being used, especially in portable products, and how they can survive the many changes they are subjected to through temperature extremes and mishandling.

Scale Review on reliability should answer many questions that you have about the assembly reliability of CSPs.

Reliability, irrespective of its definition, is no longer an "after‑the‑fact" concept; rather, it must be an integral part of development and implementation. This is especially true in the microelectronics field with its uncompromising demands for miniaturization and system integration in a faster, better and lower‑cost environment. The rapid development of CSPs and their introduction into the market is a good example of this trend.

 
Related Project(s):
EPAC (Electronic Packaging)
 
Related Area(s) of Emphasis:
System on a chip (SOC) and System in a package (SIAP) Reliability
High Density Packaging Technologies
Advanced Interconnect Reliability

 
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