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Current Silicon Die Thinning and Bonding onto Membranes Technologies for Solar Sails - Presentation
File Name: Dagostino_CurrentDieThinning.pdf | Date Submitted: 10/05/01
 

File Size:
1116KB
Document Author
Witold Sokolowski - Witold.M.Sokolowski@jpl.nasa.gov
Jet Propulsion Laboratory
Phone: 818 354-4482 | FAX: 818 393-5011
[Additional User Information]

Download "Current Silicon Die Thinning and Bonding onto Membranes Technologies for Solar Sails - Presentation" (1116KB) Now.
 
Description:
2nd Annual NEPP Conference
 
Abstract:

Authors performed a detailed review of the current technologies for thinning of silicon solid state components and available technologies for bonding a thinned die onto membrane structures. These studies were performed for the Interstellar Project with possible application in solar sail technology.

Thinning of silicon dies and bonding them into polymer membranes are one of most important and challenging enabling technologies for solar sails development. Solar sail technology will eventually allow NASA to undertake bold new missions of discovery such as searching for the signs of life on planets orbiting nearby stars, and sailing through space on beams of light to places beyond our solar system. To achieve these goals and breakthroughs in lowering the cost, launch volume, and mass of future missions, it will be necessary to develop solar sails with highly integrated multifunctional membranes consisting of embedded thin-film electronics, flexible sensors, actuators, communication and power sources. This paper examines possible technologies that are available to produce thinner dies and bond them onto membranes, evaluates performance and benefits as well as how to test, transport or handle. It concludes a thinner chip or die provides many benefits such as requiring less space, minimized thermal stresses, improved thermal/electrical performance and better power dissipation. Authors also investigates trends in electronic packaging industry and a drive to portable electronic devices, smart cards, chip-on-flex, chip-on-board etc. that forces the industry to develop thinner packages, and therefore, thinner chips. At the same time, the drive to bigger chips and lower cost per function is forcing wafers to larger diameters that causes some concerns regarding testing, handling and transport.

 
Related Project(s):
EPAR (Electronic Parts)
 
Related Area(s) of Emphasis:
Substrates and Embedded Passives Technologies
High Density Packaging Technologies
Advanced Interconnect Reliability

 
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