NEPP - Commercial Production and Manufacturability Issues

For the past few years, the semiconductor industry has tried to find a way to replace aluminum with one of the three metals that have higher conductivity: copper, silver, or gold. None of those metals is as easy to work with as aluminum. Any new material presents fresh challenges, and reliably filling sub micron holes and channels is a tough challenge in metals other than Aluminum. What's worse, those (noble) metals interact badly with silicon, diffusing into it and altering the circuit properties. Diffusion of metallization can short-circuit the chip. Cu interconnects manufacturability has had to overcome major technical challenges, among them, the development of reliable and effective diffusion barriers that could be deposited in silicon wafers along with the copper. Tantalum based diffusion barrier processing has been one of the major breakthroughs in Cu interconnect manufacturability.

In 1997, after several decades of development, IBM introduced a technology that allows chipmakers to use copper wires, rather than the traditional aluminum interconnects, to link transistors in chips. IBM has developed electroplating technology for copper that has been successfully implemented for the fabrication of chip interconnects structures. This fabrication process is known as damascene (or dual damascene). In order for a metal or alloy to be deposited on the surface of a wafer by electroplating, it is first necessary to cover the surface with a seed layer, or plating base, whose function is to conduct the current from a contact at the wafer edge to all points on the wafer where a deposit is desired. The requirement of a seed layer has led to a variety of approaches for the integration of plating; one of such approaches is illustrated in Fig. 3. Damascene plating involves deposition of the seed layer over a patterned material, which, in the case of interconnect structures, is the insulator, a functional part of the circuit that must remain in place. The plated metal covers the entire surface; excess metal must be removed by a planarization step such as chemical-mechanical polishing (CMP).

Damascene electroplating is ideally suited for the fabrication of interconnect structures, since it allows inlaying of metal simultaneously in via holes and overlying line trenches. Furthermore, it is compatible with the requirement for a barrier layer between the seed layer and the insulator; the barrier prevents interaction between the metal and the insulator.

The foremost requirement for success of the plating process (as well as for any other process of potential use in the fabrication of damascene copper interconnects) is its ability to fill trenches, vias, and their combinations completely, without any voids or seams.

Fig. 3 Process steps for the fabrication of a via and line by the dual-damascene approach. (a) Insulator deposition; (b) via definition; (c) line definition; (d) barrier and seed layer deposition; (e) plating and chemical-mechanical polishing (CMP).

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International Business Machines (IBM): The new copper interconnects were implemented initially in IBM's seventh-generation CMOS (complementary metal-oxide-semiconductor) technology. The CMOS 7S process, as it is known, showed up first in high-end products, such as chips for mainframes and the PowerPC® chips used in IBM's RS/6000® and AS/400® computers. Fig. 4 shows an electron micrograph of the SA-27 CMOS cell-based IC using copper interconnects.

Figure 4. On the left is a bird’s-eye view of the SA-27 CMOS cell-based IC using copper interconnects. A cross-section is shown to the right. The bottom layer is tungsten (W). Both are scanning electron micrographs, with color added later by IBM.

Eventually IBM expects to use the CMOS 7S in all its systems. Similarly, copper itself will become more widespread in the semiconductor industry. It is just a matter of time until all manufacturers incorporate copper interconnect technology.

Table 1. Some of the commercially available application specific integrated circuits (ASICS) that use Cu interconnects, sold by IBM. All these chips with the exception of the SA-12E use copper interconnect technology.

The available high-end chips shown in table 1 illustrate the industry trend to utilize Cu metallization for design rules below 180 nm. The main reason for this trend is that the reduced cross sectional area for interconnects to such small transistor channel length increases the parasitic resistance to an unacceptable level if Al or Al:Cu interconnects are used.

Texas Instruments: also offers products that use Cu interconnects. The SR40 High-Speed Standard Cell/ Gate Array ASIC and the GS40 low standby power ASIC are the main two families of product utilizing Cu metallization. For example, the SR40 95-Nanometer SR40 offers core logic speeds in excess of 600 MHz based on a 130-nm SIA (95-nm L (drawn)) CMOS process and utilizes a low-k dielectric and six or seven layers of second-generation dual Damascene copper interconnects

Intel Corporation: Also offers products that utilize advanced Cu interconnects, among them the Intel® Pentium® 4 processor, now available at 2.53 GHz and which has six layers of copper Interconnects. As future Intel processors inevitably offer higher clock speeds, we can expect Cu interconnects to become more and more integrated into their standard products.

Motorola – To this day (early 2003) Motorola does not appear to offer products with novel Cu interconnects, even though they were involved in the initial research and development efforts, and they have published some interesting research efforts in the area of Cu interconnects [3].