APPLICATION NOTES FOR MIL-PRF-55681

The NPSL application notes for multilayer ceramic capacitors are being amended (May 2013) to reflect the following recommendations from a NASA Engineering & Safety Center (NESC) report ^[1] on the subject of low voltage failure phenomenon of ceramic capacitors:

R-1. NASA guidelines should be amended to remove any requirements to perform Humidity Steady-State Low Voltage (HSSLV) test as an add-on lot acceptance test for MIL QPL MLCCs.

R-3. NASA guidelines should be amended to remove restrictions on MLCCs rated at less than 100 V when used in low voltage applications.

Reference:

[1] “Multilayer Ceramic Capacitors (MLCC) –Low Voltage Failure (LVF) Phenomenon” NASA/TM-2010-216852, NESC-RP-07-056, October 2010, NASA Engineering and Safety Center (NESC)

1) MIL-PRF-123 capacitors are space grade and are recommended as the first order of precedence for all Level 1 applications.

2)  The CDR02 ceramic chip capacitors are intentionally NOT listed in the NASA Parts Selection List.  This particular chip, which is offered in MIL-PRF-55681/1, has a large length to width ratio (0.18" x 0.05") which makes this chip highly susceptible to cracking as a result of board flexing.

3)  The use of ceramic chip capacitors with Termination Style "W" or "Y" is PROHIBITED.  Termination style "Y" is pure tin and termination style "W" gives the manufacturer the option to use either pure tin or a tin-lead alloy as a termination finish.  Pure tin finishes are susceptible to the growth of tin whiskers which are capable of bridging electrically isolated surfaces.  See the NPSL Prohibited Materials Section and associated references for a description of tin whiskers and the hazards they may present.

For historical reference, application notes that have been rescinded may be viewed here