APPLICATION NOTES FOR MIL-PRF-49470

The NPSL application notes for multilayer ceramic capacitors are being amended (May 2013) to reflect the following recommendations from a NASA Engineering & Safety Center (NESC) report [1] on the subject of low voltage failure phenomenon of ceramic capacitors:

R-1. NASA guidelines should be amended to remove any requirements to perform Humidity Steady-State Low Voltage (HSSLV) test as an add-on lot acceptance test for MIL QPL MLCCs.

R-3. NASA guidelines should be amended to remove restrictions on MLCCs rated at less than 100 V when used in low voltage applications.

 

Reference:

[1] “Multilayer Ceramic Capacitors (MLCC) –Low Voltage Failure (LVF) Phenomenon”  NASA/TM-2010-216852, NESC-RP-07-056, October 2010, NASA Engineering and Safety Center (NESC)

Note:  DSCC-DWG-87106 for similarly constructed parts was CANCELED Jan 2005.
 Use MIL-PRF-49470 parts as a direct replacement.

1) When available MIL-PRF-49470 SMPS capacitors are preferred over DSCC-DWG-87106 capacitors. The MIL-PRF-49470 specification was developed as part of a cooperative effort amongst the US Military, NASA and the SMPS suppliers to produce a robust replacement for the DSCC drawing. The MIL spec product provides additional quality assurance provisions which are NOT required by the DSCC drawing. Some of the benefits of the MIL-PRF-49470 product over the DSCC-DWG-87106 product include:
 

Requirement 

MIL-PRF-49470

DSCC-DWG-87106

Formal Qualification Process (QPL Established)

Yes 

No 

MIL-STD-790 Compliance

Yes 

No 

DSCC Audits

Yes 

No 

Routine Qualification Maintenance Testing (ie., Life Testing)

Yes 

No 

Group A Percent Defective Allowed (PDA) Specified

Yes 

No 

Prohibits Mixing of Chips from Different Production Lots within a Single SMPS Stack Lot

Yes 

No 

2) CAUTION! Designers must consider the geometry and relatively high mass of capacitors described by this specification. Devices which are not mounted properly may be susceptible to damage, including lead shearing, in high vibration and shock environments. The taller stacks where the stack height exceeds the minimum base dimension are particularly at risk. Special mounting techniques may be necessary to ensure safe application in these environments. Consult the manufacturer or parts engineering for recommendations to avoid potential damage from misuse of straps, coefficient of thermal expansion mismatches, etc.

3) Capacitors described by this specification are very susceptible to thermal shock damage due to their large mass of ceramic. Installation temperature profiles should provide adequate temperature rise and cool-down time to prevent damage from thermal shock.

4) Capacitors described by this specification are fragile and should be handled with extreme care. Parts which have been dropped or mishandled should be considered suspect due to the risk of microcracking which may result in latent failures.

5) The "T" Level product is recommended for all Level 1 applications.  Per MIL-PRF-49470, "T" level product requires in-process inspections and additional Group A and B screening inspections shown below that are not part of the normal "B" level flow.

"T" Level Requirements in Addition to the Normal "B" Level Requirements

In-Process Screening

  • Non-Destructive Internal Examination (Chip Level)
  • Destructive Physical Analysis (Chip Level)

Group A

  • Destructive Physical Analysis (Finished Stack Level)

Group B

  • Lot Specific Humidity, Steady-State, Low Voltage (Lot Sample Test)
  • Lot Specific Thermal Shock & Life Test (Lot Sample Test)

For historical reference, application notes that have been rescinded may be viewed here