NASA Parts Selection List (NPSL)
 Application Notes
 
Field Effect Transistor (FET)
P-Channel
 
1. Derate 3.0 mW/°C for TA > +25 °C

2. Symmetrical geometry allows operation of these devices with source/drain leads interchanged.

3. All JANTXV transistors must be PIND tested in accordance with MIL-STD-750, Method 2052, Condition A. Additional testing is not required when procured directly from the manufacturer with PIND testing in accordance with MIL-PRF-19500.
 

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