ReSpace / MAPLD 2010 Presentation Materials

** Indicates unavailable talk(s)

Monday, November 1, 2010**

Track 1 - ReSpace and Track 2 - MAPLD

Session 1- Afternoon Tutorial

1:00 pm - 5:00 pm Hansen: Space Plug-and-Play Avionics (SPA) Overview (ITAR Restricted)

6:00 pm Reception

Session 2- Afternoon Tutorial

1:00 pm - 2:15 pm Villarreal: Riverside Optimizing Compiler For Configurable Computing (ROCC)

2:30 pm - 3:45 pm Zufelt: Mini PnP ITAR Free

4:00 pm - 5:15 pm Alexander: Failure Mechanisms Affecting Performance And Longevity Of Space Electronics

6:00 pm Reception

Session 3- Afternoon Tutorial

1:00 pm - 2:15 pm Dailey: Designing FPGAs For Space - Top Down, Bottom Up, Inside Out, Etc.

2:30 pm - 3:45 pm Berg: Optimizing Mitigation Strategies For FPGA Critical Applications

4:00 pm - 5:15 pm Smith: Can You Really Design FPGAs With System Verilog?

6:00 pm Reception

Session 4 - Evening Tutorial (No Registration Required)

7:30 pm until 9:00pm Swift: Rad 101 - Introduction To Radiation Effects On Electronics

Session 5 - Evening Tutorial (No Registration Required)

7:30 pm until 9:00pm Vera: Partial Configuration

Monday | Tuesday | Wednesday | Thursday

Tuesday, November 2, 2010

Download all available Tuesday talks (ZIP file, 60MB)

Track 1 - ReSpace and Track 2 - MAPLD

Session - Plenary

7:00 am Breakfast

8:00 am - 8:15 am Suddarth: Opening Remarks**

8:15 am - 8:45 am Abbot: History Of Surrey**

8:45 am - 9:15 am Puig-Suari: History Of Cube Sats**

9:15 am - 9:45 am Nixon:Small Sats, Electronics and "Wicked" Problems**

9:45 am - 10:15 am Break

10:15 am - 10:30 am Powell: NASA Opening Remarks**

10:30 am - 11:00 am Troxel: Trends In Reconfigurable And High Performance Electronics For Space**

11:00 am - 11:30 am Lyke: Space Plug-and-play Avionics (SPA)

11:30 am - 12:15 pm Break

12:15 pm Lunch and Panel Session (Are You Crazy Flying That?)-Panel Moderator: Ken LaBel, NASA

Track 1 - ReSpace

Session I - SPA Standardization

1:30 pm - 2:00 pm Howe: Kit Of Parts Architecture**

2:00 pm - 2:30 pm
Hansen / Graven: GNC Hierarchy Using SPA

2:30 pm - 3:00 pm
Christensen / Cannon: SPA Network Management**

3:00 pm - 3:30 pm Break

3:30 pm - 4:00 pm Schenk: Advanced Plug - n - Play Technologies (APT) Lessons Learned

4:00 pm - 5:30 pm Making SPA Work: Industry Input, the Standards Process, and Where we are Now - Panel Chair: Millay Morgan, APT**

6:15 pm Dinner - "Meet The Experts"

Track 2 - MAPLD

Session A - Mil / Aero Market Update For FPGAs And Associated Devices

1:30 pm - 1:40 pm
Ward: Non-Volatile And Volatile Carbon Nanotube Electronics For Reconfigurable, Radiation Hard Space Based Applications**

1:40 pm - 1:50 pm
Wang: Very High Density and Radiation Tolerant PROM For Space Syatems

1:50 pm - 2:00 pm Philpy: 90nm Design-Hardened Structured ASIC; The Next Generation of Digital ICs for Space

2:00 pm - 2:10 pm Wolday: Actel's RTAX4000D Space Qualification Update

2:10 pm - 2:20 pm Katzman: Space Qualified Ultra-High Speed Plug-and Play Radiation Hard SERDES

2:20 pm - 2:30 pm Lake: Aeroflex Non-Volatile Boot Memory For Xilinx FPGAs

2:30 pm - 2:40 pm Swonger: Radiation Hardened Integrated Point-of-load DC-DC Converter On Sapphire

2:40 pm - 2:50 pm Puchner: High Speed Radiation Hard 72Mbit Quad Data Rate SRAM For Space Applications

2:50 pm - 3:00 pm Carmichael: Introducing The Virtex-5QV Reconfigurable FPGA: The Biggest And Fastest Space-grade Part On The Planet**

3:00 pm - 3:30 pm Break

3:30 pm - 3:40 pm Ginosar: JPIC - Rad-Hard JPEG2000 Image Compression ASIC

3:40 pm - 3:50 pm Bancelin: ATMEL ATF280F Rad Hard SRAM Based Dynamic Partial Reconfiguration

3:50 pm - 4:00 pm Jones: The Advantages And Challenges Of Using Many-core Processors For Space-based Applications

4:00 pm - 4:10 pm Elftmann: RadRunner

Session B -Flight / Field Plans And Experiences With FPGAs And PLDs

4:10 pm - 4:30 pm Hodson: LIDAR Image processing acceleration via FPGA implementation

4:30 pm - 4:50 pm Espinosa: SpaceCube On-Board Science Data Processor: Current Applications and Future Architectures

4:50 pm - 5:10 pm Morgan: LANL Cube Sat Reconfigurable Computer (CRC)

5:10 pm - 5:30 pm Howard: Highly Scalable/Highly Configurable FPGA Based Solid State Recorder For Multi-Mission Space Applications

6:15 pm Dinner - "Meet The Experts"

Monday | Tuesday | Wednesday | Thursday

Wednesday, November 3, 2010

Download all available Wednesday talks (ZIP file, 160MB)

Track 1 - ReSpace and Track 2 - MAPLD

Session II -Combined Session - Software Defined Radio

7:00 am Breakfast

8:30 am - 8:50 am Reinhart: Development Of NASA's Space Communications And Navigation Test Bed Aboard ISS To Investigate SDR, On-board Networking And Navigation Technologies**

8:50 am - 9:10 am Palmer: The Firehose AdaptiveÂ Software DefinedÂ Radio

9:10 am - 9:30 am Mast: Software Defined Payloads

9:30 am - 10:00 am Kief: GENSO, CubeSats and Space Dial Tone

10:00 am - 10:30 am Break

10:30 am - 10:50 am Sauer: Research And Development Of A Flexible Communication Platform For Space

10:50 am - 11:10 am Wyglinski: Responsive Satellite Communications Via FPGA-Based Software-Defined Radio For SPA-U Compatible Platforms

11:10 am - 11:30 am Lynaugh: Software Defined Radio

11:30 am - 12:15 pm Break

12:15 pm Lunch

Track 1 - ReSpace

Session III -New Architectures For Aerospace

1:30 pm - 2:00 pm Phidget: Turning Vision Into Reality

2:00 pm - 2:30 pm Boesen: Integration Of The Self-Healing eDNA Architecture In An Embedded System And Evaluation Of A Fourier Transform Spectrometer Instrument Application

2:30 pm - 3:00 pm
Eddy: AFRL's AI & T Tool Flow Software

3:00 pm - 3:30 pm Lai: Next Generation Plug n' Play Radiation Tolerant Avionics

3:30 pm - 4:00 pm Break

4:00 pm - 4:30 pm Ardalan: On-demand On-line Scrubbing Of The RHBD Structured ASIC AppliquÃ© Sensor Interface Module**

4:30 pm - 5:00 pm Martin: Spacecraft Plug and Play Avionics Experiment - On Orbit Results**

5:00 pm - 5:30 pm Bruhn: Introducing A Low Cost and High Performing Interoperable Satellite Platform Based OnÂ Plug-and-Play Technology For ModularÂ and ReconfigurableÂ Civilian AndÂ Military Nanosatellites

5:30 pm - 6:00 pm McGuirk - LV SPA

6:30 pm Dinner - Speaker: Hon. Heather Wilson, Former U.S. Representative, NM 1st Congressional District

Track 2 - MAPLD

Session B - Flight / Field Plans And Experiences With FPGAs And PLDs (contd...from Tuesday)

1:30 pm - 1:50 pm
Bradley: Field Programmable Gate Array (FPGA)-Based Digital Signal Processor (DSP) For The NASA Soil Moisture Active Passive (SMAP) Radio-frequency Interference (RFI) Mitigating Radiometer

1:50 pm - 2:10 pm
Jones: HXiS: The HyperX Processor in Space

2:10 pm - 2:30 pm Kalb: Flexible Space Computing Architectures and the Role of FPGAs

Session C - Verification And Validation Of FPGAs and PLDs

2:30 pm - 2:50 pm Black: Impact Of Ion-Induced Meta-Stable Conditions On Clocked Operations Of DICE Flip-Flops For Reconfigurable Devices

2:50 pm - 3:10 pm Monson: Fault Injection Results Of Linux On An FPGA Embedded Platform

3:10 pm - 3:30 pm Bit-Accurate, At-Speed Hardware Verification For DO-254 Compliance

3:30 pm - 4:00 pm Break

4:00 pm - 4:20 pm McGuffey: A comparison of the effectiveness of SEE Mitigation On RTAX-S/SL And ProASIC3E FPGAs

4:20 pm - 4:40 pm Iturbe: R3TOS - Reliable Scheduling and Allocation of Real-time Hardware Tasks onto Partially Damaged Xilinx FPGAs

4:40 pm - 5:00 pm Abdallah: The Challenge Of Hold Time Check In Timing Critical FPGA Designs

5:00 pm - 5:20 pm Figueiredo: Developing A Framework For Independent Validation And Verification Of Complex Space FPGAs For NASA Spacecrafte

6:30 pm Dinner - Speaker: Hon. Heather Wilson, Former U.S. Representative, NM 1st Congressional District

Monday | Tuesday | Wednesday | Thursday

Thursday, November 4, 2010

Download all available Thursday talks (ZIP file, 23MB)

Track 1 - ReSpace

Session IV -On The Horizon

7:30 am Breakfast

8:30 am - 8:50 am Furano: CANopen Networks As An Enabler For Modern Space-Borne Control Systems: The European Space Agencyâ€™s Perspective

8:50 am - 9:10 am Vahid - Composing Video/Sensor-Based Automated Notification Systems Using Spatial Programming

9:10 am - 9:30 am Wender: Monolithic-MCM Analog IC Design For Space**

9:30 am - 10:00 am Anderson: Psoc**

10:00 am - 10:30 am Break

10:30 am - 10:50 am Santangelo: QuickSAT and theÂ step_SATdb database, a web based and open source concurrent satellite design automation environment**

10:50 am - 11:10 am Pattichis: Adaptive Wiring Manifold**

11:10 am - 11:30 am Sharma: A Virus-Based Transistor For Integrated Molecular-Scale Circuits**

11:50 am Lunch, Closing

Track 2 - MAPLD

Session D - Designing with FPGAs and PLDs

7:30 am Breakfast

8:30 am - 8:50 am Habinc: Implementing SpaceWire Routers As Standard Products Using FPGA Technology

8:50 am - 9:10 am Wirthlin: Dynamic Partial Reconfiguration Of Softcore Processors On The Virtex 5

9:10 am - 9:30 am
Platzker: FPGA SynthesisBased Radiation Effects Mitigation Using Triple Modular Redundancy And Safe FSM Implementations

9:30 am - 9:50 am Walters: Radiation Hardening By Software For The Embedded PowerPC, Preliminary Findings

9:50 am - 10:10 am Nguyen: Actel RTAX-DSP Design Techniques For High Reliability Application

10:10 am - 10:30 am Break

10:30 am - 10:50 am Smith: Applying Modern Verification Methods To VHDL Designs

10:50 am - 11:10 am Wang: Design Choices And Guidelines For Configuration Monitoring And Management Of The RHBD Virtex-5QV Space-grade FPGA

11:10 am - 11:30 am Swift: Prototyping V-5QV Space Applications Using The Commercial-Grade FPGAs And Boards

11:30 am - 11:50 am Ginosar: A Design Flow For FPGA Conversion Into Radiation-Hardened ASIC

11:50 am Lunch, Closing

Monday | Tuesday | Wednesday | Thursday

Session 1- Afternoon Tutorial
1:00 pm - 5:00 pm	Hansen: Space Plug-and-Play Avionics (SPA) Overview (ITAR Restricted)
6:00 pm	Reception
Session 2- Afternoon Tutorial
1:00 pm - 2:15 pm	Villarreal: Riverside Optimizing Compiler For Configurable Computing (ROCC)
2:30 pm - 3:45 pm	Zufelt: Mini PnP ITAR Free
4:00 pm - 5:15 pm	Alexander: Failure Mechanisms Affecting Performance And Longevity Of Space Electronics
6:00 pm	Reception
Session 3- Afternoon Tutorial
1:00 pm - 2:15 pm	Dailey: Designing FPGAs For Space - Top Down, Bottom Up, Inside Out, Etc.
2:30 pm - 3:45 pm	Berg: Optimizing Mitigation Strategies For FPGA Critical Applications
4:00 pm - 5:15 pm	Smith: Can You Really Design FPGAs With System Verilog?
6:00 pm	Reception

Session 4 - Evening Tutorial (No Registration Required)
7:30 pm until 9:00pm	Swift: Rad 101 - Introduction To Radiation Effects On Electronics
Session 5 - Evening Tutorial (No Registration Required)
7:30 pm until 9:00pm	Vera: Partial Configuration

Session - Plenary
7:00 am	Breakfast
8:00 am - 8:15 am	Suddarth: Opening Remarks**
8:15 am - 8:45 am	Abbot: History Of Surrey**
8:45 am - 9:15 am	Puig-Suari: History Of Cube Sats**
9:15 am - 9:45 am	Nixon:Small Sats, Electronics and "Wicked" Problems**
9:45 am - 10:15 am	Break
10:15 am - 10:30 am	Powell: NASA Opening Remarks**
10:30 am - 11:00 am	Troxel: Trends In Reconfigurable And High Performance Electronics For Space**
11:00 am - 11:30 am	Lyke: Space Plug-and-play Avionics (SPA)
11:30 am - 12:15 pm	Break
12:15 pm	Lunch and Panel Session (Are You Crazy Flying That?)-Panel Moderator: Ken LaBel, NASA

Session I - SPA Standardization
1:30 pm - 2:00 pm	Howe: Kit Of Parts Architecture**
2:00 pm - 2:30 pm	Hansen / Graven: GNC Hierarchy Using SPA
2:30 pm - 3:00 pm	Christensen / Cannon: SPA Network Management**
3:00 pm - 3:30 pm	Break
3:30 pm - 4:00 pm	Schenk: Advanced Plug - n - Play Technologies (APT) Lessons Learned
4:00 pm - 5:30 pm	Making SPA Work: Industry Input, the Standards Process, and Where we are Now - Panel Chair: Millay Morgan, APT**
6:15 pm	Dinner - "Meet The Experts"

Session A - Mil / Aero Market Update For FPGAs And Associated Devices
1:30 pm - 1:40 pm	Ward: Non-Volatile And Volatile Carbon Nanotube Electronics For Reconfigurable, Radiation Hard Space Based Applications**
1:40 pm - 1:50 pm	Wang: Very High Density and Radiation Tolerant PROM For Space Syatems
1:50 pm - 2:00 pm	Philpy: 90nm Design-Hardened Structured ASIC; The Next Generation of Digital ICs for Space
2:00 pm - 2:10 pm	Wolday: Actel's RTAX4000D Space Qualification Update
2:10 pm - 2:20 pm	Katzman: Space Qualified Ultra-High Speed Plug-and Play Radiation Hard SERDES
2:20 pm - 2:30 pm	Lake: Aeroflex Non-Volatile Boot Memory For Xilinx FPGAs
2:30 pm - 2:40 pm	Swonger: Radiation Hardened Integrated Point-of-load DC-DC Converter On Sapphire
2:40 pm - 2:50 pm	Puchner: High Speed Radiation Hard 72Mbit Quad Data Rate SRAM For Space Applications
2:50 pm - 3:00 pm	Carmichael: Introducing The Virtex-5QV Reconfigurable FPGA: The Biggest And Fastest Space-grade Part On The Planet**
3:00 pm - 3:30 pm	Break
3:30 pm - 3:40 pm	Ginosar: JPIC - Rad-Hard JPEG2000 Image Compression ASIC
3:40 pm - 3:50 pm	Bancelin: ATMEL ATF280F Rad Hard SRAM Based Dynamic Partial Reconfiguration
3:50 pm - 4:00 pm	Jones: The Advantages And Challenges Of Using Many-core Processors For Space-based Applications
4:00 pm - 4:10 pm	Elftmann: RadRunner
Session B -Flight / Field Plans And Experiences With FPGAs And PLDs
4:10 pm - 4:30 pm	Hodson: LIDAR Image processing acceleration via FPGA implementation
4:30 pm - 4:50 pm	Espinosa: SpaceCube On-Board Science Data Processor: Current Applications and Future Architectures
4:50 pm - 5:10 pm	Morgan: LANL Cube Sat Reconfigurable Computer (CRC)
5:10 pm - 5:30 pm	Howard: Highly Scalable/Highly Configurable FPGA Based Solid State Recorder For Multi-Mission Space Applications
6:15 pm	Dinner - "Meet The Experts"

Session II -Combined Session - Software Defined Radio
7:00 am	Breakfast
8:30 am - 8:50 am	Reinhart: Development Of NASA's Space Communications And Navigation Test Bed Aboard ISS To Investigate SDR, On-board Networking And Navigation Technologies**
8:50 am - 9:10 am	Palmer: The Firehose AdaptiveÂ Software DefinedÂ Radio
9:10 am - 9:30 am	Mast: Software Defined Payloads
9:30 am - 10:00 am	Kief: GENSO, CubeSats and Space Dial Tone
10:00 am - 10:30 am	Break
10:30 am - 10:50 am	Sauer: Research And Development Of A Flexible Communication Platform For Space
10:50 am - 11:10 am	Wyglinski: Responsive Satellite Communications Via FPGA-Based Software-Defined Radio For SPA-U Compatible Platforms
11:10 am - 11:30 am	Lynaugh: Software Defined Radio
11:30 am - 12:15 pm	Break
12:15 pm	Lunch

Session III -New Architectures For Aerospace
1:30 pm - 2:00 pm	Phidget: Turning Vision Into Reality
2:00 pm - 2:30 pm	Boesen: Integration Of The Self-Healing eDNA Architecture In An Embedded System And Evaluation Of A Fourier Transform Spectrometer Instrument Application
2:30 pm - 3:00 pm	Eddy: AFRL's AI & T Tool Flow Software
3:00 pm - 3:30 pm	Lai: Next Generation Plug n' Play Radiation Tolerant Avionics
3:30 pm - 4:00 pm	Break
4:00 pm - 4:30 pm	Ardalan: On-demand On-line Scrubbing Of The RHBD Structured ASIC AppliquÃ© Sensor Interface Module**
4:30 pm - 5:00 pm	Martin: Spacecraft Plug and Play Avionics Experiment - On Orbit Results**
5:00 pm - 5:30 pm	Bruhn: Introducing A Low Cost and High Performing Interoperable Satellite Platform Based OnÂ Plug-and-Play Technology For ModularÂ and ReconfigurableÂ Civilian AndÂ Military Nanosatellites
5:30 pm - 6:00 pm	McGuirk - LV SPA
6:30 pm	Dinner - Speaker: Hon. Heather Wilson, Former U.S. Representative, NM 1st Congressional District

Session B - Flight / Field Plans And Experiences With FPGAs And PLDs (contd...from Tuesday)
1:30 pm - 1:50 pm	Bradley: Field Programmable Gate Array (FPGA)-Based Digital Signal Processor (DSP) For The NASA Soil Moisture Active Passive (SMAP) Radio-frequency Interference (RFI) Mitigating Radiometer
1:50 pm - 2:10 pm	Jones: HXiS: The HyperX Processor in Space
2:10 pm - 2:30 pm	Kalb: Flexible Space Computing Architectures and the Role of FPGAs
Session C - Verification And Validation Of FPGAs and PLDs
2:30 pm - 2:50 pm	Black: Impact Of Ion-Induced Meta-Stable Conditions On Clocked Operations Of DICE Flip-Flops For Reconfigurable Devices
2:50 pm - 3:10 pm	Monson: Fault Injection Results Of Linux On An FPGA Embedded Platform
3:10 pm - 3:30 pm	Bit-Accurate, At-Speed Hardware Verification For DO-254 Compliance
3:30 pm - 4:00 pm	Break
4:00 pm - 4:20 pm	McGuffey: A comparison of the effectiveness of SEE Mitigation On RTAX-S/SL And ProASIC3E FPGAs
4:20 pm - 4:40 pm	Iturbe: R3TOS - Reliable Scheduling and Allocation of Real-time Hardware Tasks onto Partially Damaged Xilinx FPGAs
4:40 pm - 5:00 pm	Abdallah: The Challenge Of Hold Time Check In Timing Critical FPGA Designs
5:00 pm - 5:20 pm	Figueiredo: Developing A Framework For Independent Validation And Verification Of Complex Space FPGAs For NASA Spacecrafte
6:30 pm	Dinner - Speaker: Hon. Heather Wilson, Former U.S. Representative, NM 1st Congressional District

Session IV -On The Horizon
7:30 am	Breakfast
8:30 am - 8:50 am	Furano: CANopen Networks As An Enabler For Modern Space-Borne Control Systems: The European Space Agencyâ€™s Perspective
8:50 am - 9:10 am	Vahid - Composing Video/Sensor-Based Automated Notification Systems Using Spatial Programming
9:10 am - 9:30 am	Wender: Monolithic-MCM Analog IC Design For Space**
9:30 am - 10:00 am	Anderson: Psoc**
10:00 am - 10:30 am	Break
10:30 am - 10:50 am	Santangelo: QuickSAT and theÂ step_SATdb database, a web based and open source concurrent satellite design automation environment**
10:50 am - 11:10 am	Pattichis: Adaptive Wiring Manifold**
11:10 am - 11:30 am	Sharma: A Virus-Based Transistor For Integrated Molecular-Scale Circuits**
11:50 am	Lunch, Closing

Session D - Designing with FPGAs and PLDs
7:30 am	Breakfast
8:30 am - 8:50 am	Habinc: Implementing SpaceWire Routers As Standard Products Using FPGA Technology
8:50 am - 9:10 am	Wirthlin: Dynamic Partial Reconfiguration Of Softcore Processors On The Virtex 5
9:10 am - 9:30 am	Platzker: FPGA SynthesisBased Radiation Effects Mitigation Using Triple Modular Redundancy And Safe FSM Implementations
9:30 am - 9:50 am	Walters: Radiation Hardening By Software For The Embedded PowerPC, Preliminary Findings
9:50 am - 10:10 am	Nguyen: Actel RTAX-DSP Design Techniques For High Reliability Application
10:10 am - 10:30 am	Break
10:30 am - 10:50 am	Smith: Applying Modern Verification Methods To VHDL Designs
10:50 am - 11:10 am	Wang: Design Choices And Guidelines For Configuration Monitoring And Management Of The RHBD Virtex-5QV Space-grade FPGA
11:10 am - 11:30 am	Swift: Prototyping V-5QV Space Applications Using The Commercial-Grade FPGAs And Boards
11:30 am - 11:50 am	Ginosar: A Design Flow For FPGA Conversion Into Radiation-Hardened ASIC
11:50 am	Lunch, Closing